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[VHDL-FPGA-Verilog] ADC0809

Description: adc0809数模转换芯片fpga控制程序
Platform: | Size: 57344 | Author: conanhfl | Hits:

[VHDL-FPGA-Verilog] ADC1

Description: 用FPGA实现的ADC采样器，用VHDL编写，8个模拟信号通道地址,8位数据输出-Using FPGA to achieve the ADC sampler, using VHDL prepared 8-channel analog signal address, 8-bit data output
Platform: | Size: 124928 | Author: 叶开 | Hits:

[VHDL-FPGA-Verilog] 50vvoltmeter

Description:
Platform: | Size: 138240 | Author: 丁珊珊 | Hits:

[SCM] MSP430F149_IIC_DAC5571

Description: 本源码维MSP430F149控制IIC协议的AD芯片DAC5571，并再1602液晶上显示数据 MCU的P1.0、P1.1 端口与DAC5571 的SDA、SCK端口连接，通过在两个GPIO上模拟 I2C时序从而实现对DAC的操作。可以看到，DAC5571 的输出端Vout连接到了跳线座P7 的第 1 脚。如果用短路帽将跳线座J1 的 2 脚 和 3 脚连接，则DAC的输出直接驱动LED，可以通过LED亮度的变化直观地观察到 DAC输出电压值的变化；如果用短路帽将跳线座J1 的2 脚和1 脚连接，则可以用 MSP430 内置的ADC对DAC输出的电压进行采样转换，对ADC和DAC电路同时进行应用。-MSP430F149-dimensional control of the source of the AD Agreement IIC chip DAC5571, and another 1602 on the display data LCD MCU of P1.0, P1.1 ports of the DAC5571 and SDA, SCK-port connectivity, through two GPIO on I2C timing simulation in order to achieve DAC operation. Can be seen, DAC5571 output Vout is connected to a jumper P7 Block 1 foot. If the cap will short-circuit jumper J1 Block, 2 pin and 3 pin connection, the DAC output to directly drive LED, through the LED brightness can be visually observed changes in DAC output voltage changes in value If the cap will short-circuit jumper Block J1 2 feet and 1 foot to connect, you can use the built-in ADC of the MSP430 output voltage DAC sampling conversion of ADC and DAC circuit applications at the same time.
Platform: | Size: 35840 | Author: skywalker | Hits:

[Communication-Mobile] 13898375FPGA_FIR

Description: 尽管频率合成技术已经经历了大半个世纪的发展史，但直到今天，人们对 它的研究仍然在继续。现在，我们可以开发出输出频率高达IG的DDS系统， 武汉理工大学硕士学位论文 已能满足绝大多数频率源的要求，集成DDS产品的信噪比也可达到75dB以上， 已达到锁相频率合成的一般水平。电子技术的发展己进入数字时代，模拟信号 数字化的方法也是目前一个热门研究课题，高速AD、DA器件在通信、广播电 视等领域的应用越来越广泛。本次设计完成了软件仿真和硬件实现，对设计原 理和设计结果进行了一定的理论分析，在一定的频率范围内设计结果与理论值 基本符号，达到了设计指标的要求。限于本人的水平和实现条件，此次设计在 频率稳定度、最高输出频率、降低杂散等方面仍有改进的空间，今后还需进一 步提高。
Platform: | Size: 152576 | Author: 包真 | Hits:

[VHDL-FPGA-Verilog] ADC

Description: 用verilog编程实现的基于FPGA的AD数据采集程序-Verilog Programming with FPGA-based data collection procedures AD
Platform: | Size: 499712 | Author: 张西贝 | Hits:

[VHDL-FPGA-Verilog] AD9863_if_old-2005-5-8

Description: fpga开发的程序，内容都不错，主要是ad-FPGA development process, the contents are good, mainly ad
Platform: | Size: 1024 | Author: bob | Hits:

[VHDL-FPGA-Verilog] adc_control

Description: Xilinx FPGA 开发板的ADC采样源程序 内有PDF文档详细说明 VHDL代码-Xilinx FPGA development board with the ADC sampling source has a detailed description PDF document VHDL code
Platform: | Size: 951296 | Author: visual | Hits:

[VHDL-FPGA-Verilog] fpga-pulse_sequence

Description: pulse_sequence.vhd 并行脉冲控制器 light.vhd.vhd 交通脉冲控制器 division1.vhd 电压脉冲控制器中的分频 ad.vhd 电压脉冲控制器中的A/D控制 code.vhd 电压脉冲控制器中的脉冲运算模块 voltage2.bdf 电压脉冲控制系统-pulse_sequence.vhd pulse controller parallel light.vhd.vhd traffic controller division1.vhd pulse voltage pulse controller ad.vhd sub-frequency voltage pulse controller A/D control code.vhd voltage pulse of the pulse controller computing module voltage2.bdf voltage pulse control system
Platform: | Size: 6144 | Author: libing | Hits:

[Embeded-SCM Develop] r_w_flash

Description: FPGA高速完成AD采集回来的数据进行高速读写FLASH存储-AD Acquisition completion of FPGA high-speed data back to high-speed read and write FLASH memory
Platform: | Size: 901120 | Author: 王瓶 | Hits:

[Embeded-SCM Develop] AIC

Description: 使用FPGA/CPLD设置语音AD、DA转换芯片AIC23，FPGA/CPLD系统时钟为24.576MHz 1、AIC系统时钟为12.288MHz，SPI时钟为6.144MHz 2、AIC处于主控模式 3、input bit length 16bit output bit length 16bit MSB first 4、帧同步在96KHz-The use of FPGA/CPLD set voice AD, DA conversion chip AIC23, FPGA/CPLD system clock for the 24.576MHz 1, AIC system clock is 12.288MHz, SPI clock is 6.144MHz 2, AIC is in master mode 3, input bit length 16bit output bit length 16bit MSB first 4, frame synchronization at 96KHz
Platform: | Size: 2048 | Author: 张键 | Hits:

[VHDL-FPGA-Verilog] Simulate

Description: FPGA控制AD逐点采集信号，并将AD转换后的数据串行发送出去。-FPGA to control the signal sampling point by point AD, AD conversion and serial data sent.
Platform: | Size: 1024 | Author: Hongjun | Hits:

[VHDL-FPGA-Verilog] TLC0831

Description: FPGA对TLC0831的控制程序，实现AD的转换控制和数据的读取。-FPGA control procedures of the TLC0831 to achieve AD conversion control and data read.
Platform: | Size: 2048 | Author: 原腾飞 | Hits:

[VHDL-FPGA-Verilog] daima

Description: 状态机控制AD转换模块 该模块主要实现对MAX197的控制：根据设计需要对芯片进行初始化（包括写控制字选择输入电压值范围、选择通道以及工作模式），并把通道数送指示灯显示以及用键盘控制通道号（按一下，通道号加1，同时点亮相应的指示灯，循环使用个通道）；控制状态机的工作时序，并置两次采集到的数据为12位数据输出，并经过锁存进程来锁存数据，最后从锁存器中把输出数据-The state machine controls AD and changes the module this module mainly realizes the control on MAX197: According to designing the need to initialize the chip (including writing the word of controlling and choosing to input the value range of the voltage, choose the passway and work pattern), count, give passway
Platform: | Size: 3072 | Author: 万俟斌 | Hits:

[Other] DVDT_MORE

Description: 基于FPGA有限状态机的数据采集系统，实现对高速AD转换的控制。-FPGA-based finite state machine of the data acquisition system for high-speed AD conversion control.
Platform: | Size: 389120 | Author: blackstar1 | Hits:

[VHDL-FPGA-Verilog] HighSpeedAD

Description: 基于FPGA数据采集系统，用VHDL语言描述，实现对高速AD转换的控制。-FPGA-based data acquisition system, described by VHDL language to realize high-speed AD conversion control.
Platform: | Size: 113664 | Author: blackstar1 | Hits:

[VHDL-FPGA-Verilog] EP1C3_12_5_RSV

Description: 基于ＦＰＧＡ的数字存储示波器，用ＶＨＤＬ实现的，压缩包里是Quartus工程。AD采样送进FPGA，存入SRAM后用DA在普通示波器上可以显示。-FPGA-based digital storage oscilloscope, using VHDL achieved compression is Quartus project bag. AD sample into FPGA, after SRAM into DA in ordinary oscilloscope can display.
Platform: | Size: 61440 | Author: deadtomb | Hits:

[Other] EP1C3_12_7_SPCTR

Description: 基于FPGA的信号采集及频谱分析，用VHDL编写，压缩包里是Quartus下的工程。AD采样用状态机实现，并存入LPM_RAM。设计了一个UART模块（也是状态机实现的），可将数据发到ＰＣ机上。-FPGA-based signal acquisition and spectral analysis, prepared with VHDL, Quartus compression bag is the next project. AD sampling state machine used to achieve, and deposited LPM_RAM. The design of a UART module (state machine is realized), the data can be sent to the PC machine.
Platform: | Size: 214016 | Author: deadtomb | Hits:

[VHDL-FPGA-Verilog] TLC5510A

Description:
Platform: | Size: 1472512 | Author: 陈宇 | Hits:

[VHDL-FPGA-Verilog] slave_spi_ctrl

Description: SPI 的FPGA控制源代码，用于一般通用的SPI技术，FPGA/CPLD控制的AD数据采集-SPI control course code
Platform: | Size: 1024 | Author: luxiaogang | Hits:
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